Module 14: "Directory-based Cache Coherence"
  Lecture 30: "SGI Origin 2000"
 

Cache and dir. states

  • Cache states: MESI
  • Six directory states (may not be six bits)
    • Unowned (I): no cache has a copy, memory copy is valid
    • Shared (S): one or more caches have copies, memory copy is valid
    • Dirty exclusive (M or DEX): exactly one cache has block in M or E state
      • Directory cannot distinguish between M and E
    • Two pending or busy or transient states (PSH and PDEX): a transaction for the cache block is in progress; home cannot accept any new request
    • Poisoned state: used for efficient page migration

Handling a read miss

  • Origin protocol does not assume anything about ordering of messages in the network
  • At requesting hub
    • Address is decoded and home is located
    • Request forwarded to home if home is remote
  • At home
    • Directory lookup and data lookup are initiated in parallel
    • Directory banks are designed to be slightly faster than other banks
    • The directory entry may reveal several possible states
      • Actions taken depends on this
  • Directory state lookup
    • Unowned: mark directory to point to requester, state becomes M, send cache line
    • Shared: mark directory bit, send cache line
    • Busy: send NACK to requester
    • Modified: if owner is not home, forward to owner
    • 3-hop vs. 4-hop reply?
    • Origin has only two virtual networks available to protocol
      • How to handle interventions?
  • Directory state M
    • Actions at home: set PSH state, set the vector with two sharers, NACK all subsequent requests until state is S
    • Actions at owner: if cache state is M send reply to requester (how to know who the requester is?) and send sharing writeback (SWB) to home; if cache state is E send completion messages to requester and home (no data is sent); in all cases cache state becomes S
    • Sharing writeback or completion message, on arrival at home, changes directory state to S
    • If the owner state is E, how does the requester get the data?
      • The famous speculative reply of Origin 2000
      • Note how processor design (in this case MIPS R10k) influences protocol decisions