Module 12: "Multiprocessors on a Snoopy Bus"
  Lecture 26: "Case Studies"
 

SGI Challenge

  • Supports 36 MIPS R4400 (4 per board) or 18 MIPS R8000 (2 per board)
  • A-chip has the address bus interface, request table
  • CC-chip handles coherence through the duplicate set of tags
  • Each D-chip handles 64 bits of data and as a whole 4 D-chips interface to a 256-bit wide data bus

Sun Enterprise

  • Supports up to 30 UltraSPARC processors
  • 2 processors and 1 GB memory per board
  • Wide 64-byte memory bus and hence two memory cycles to transfer the entire cache line (128 bytes)

Sun Gigaplane bus

  • Split-transaction, 256 bits data, 41 bits address, 83.5 MHz (compare to 47.6 MHz of SGI Powerpath-2)
  • Supports 16 boards
  • 112 outstanding transactions (up to 7 from each board)
  • Snoop result is available 5 cycles after the request phase
  • Memory fetches data speculatively
  • MOESI protocol