Dependence graph

• Now we have four queues
  • Processor request (PR) and intervention reply (IY) are L1 to L2
  • Processor reply (PY) and intervention request (IR) are L2 to L1

• Possible to combine PR and IY into a supernode of the graph and still be cycle-free
  • Leads to one L1 to L2 queue
• Similarly, possible to combine IR and PY into a supernode
  • Leads to one L2 to L1 queue
• Cannot do both
  • Leads to cycle as already discussed
• Bottomline: need at least three queues for two-level cache hierarchy

Multiple outstanding requests

• Today all processors allow multiple outstanding cache misses
  • We have already discussed issues related to ooo execution
  • Not much needs to be added on top of that to support multiple outstanding misses
  • For multi-level cache hierarchy the queue depths may be made bigger for performance reasons
  • Various other buffers such as writeback buffer need to be made bigger