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Bus interface logic
A request table entry is freed when the response is observed on the bus
Snoop results
- Three snoop wires: shared, modified, inhibit (all wired-OR)
- The inhibit wire helps in holding off snoop responses until the data response is launched on the bus
- Although the request phase determines who will source the data i.e. some cache or memory, the memory controller does not know it
- The cache with a modified copy keeps the inhibit line asserted until it gets the data bus and flushes the data; this prevents memory controller from sourcing the data
- Otherwise memory controller arbitrates for the data bus
- When the data appears all cache controllers appropriately assert the shared and modified line
- Why not launch snoop results as soon as they are available?
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