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SGI Powerpath-2 bus
- Essentially two main buses and various control wires for snoop results, flow control etc.
- Address bus: five cycle arbitration, used during request
- Data bus: five cycle arbitration, five cycle transfer, used during response
- Three different transactions may be in one of these three phases at any point in time
- Forming a total order
- After the decode cycle during request phase every cache controller takes appropriate coherence actions i.e. BusRd downgrades M line to S, BusRdX invalidates line
- If a cache controller does not get the tags due to contention with the processor; it simply lengthens the ack phase beyond one cycle
- Thus the total order is formed during the request phase itself i.e. the position of each request in the total order is determined at that point
- BusWB case
- BusWB only needs the request phase
- However needs both address and data lines together
- Must arbitrate for both together
- BusUpgr case
- Consists only of the request phase
- No response or acknowledgment
- As soon as the “ack” phase of address arbitration is completed by the issuing node, the upgrade has sealed a position in the total order and hence is marked complete by sending a completion signal to the issuing processor by its local bus controller (each node has its own bus controller to handle bus requests)
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