Moore’s Law:

• Number of transistors on-chip doubles every 18 months
  • So much of innovation was possible only because we had transistors
  • Phenomenal 58% performance growth every year
• Moore’s Law is facing a danger today
  • Power consumption is too high when clocked at multi-GHz frequency and it is proportional to the number of switching transistors
• Wire delay doesn’t decrease with transistor size

Scaling Issues:

• Hardware for extracting ILP has reached the point of diminishing return
  • Need a large number of in-flight instructions
  • Supporting such a large population inside the chip requires power-hungry delay-sensitive logic and storage
  • Verification complexity is getting out of control
• How to exploit so many transistors?
  • Must be a de-centralized design which avoids long wires

Multi-core:

• Put a few reasonably complex processors or many simple processors on the chip
  • Each processor has its own primary cache and pipeline
  • Often a processor is called a core
  • Often called a chip-multiprocessor (CMP)
• Did we use the transistors properly?
  • Depends on if you can keep the cores busy
  • Introduces the concept of thread-level parallelism (TLP)