Multiple Issue:

Out-of-order Multiple Issue:

• Some hardware nightmares
  • Complex issue logic to discover independent instructions
  • Increased pressure on cache
• Impact of a cache miss is much bigger now in terms of lost opportunity
• Various speculative techniques are in place to “ignore” the slow and stupid memory
• Increased impact of control dependence
• Must feed the processor with multiple correct instructions every cycle
• One cycle of bubble means lost opportunity of multiple instructions
• Complex logic to verify