- : This input is tested by “ WAIT ” instruction. If the TEST input goes low; execution will continue. Else the processor remains in an idle state.

NMI - Non-maskable Interrupt: The non-maskable interrupt input is similar to INTR except that the NMI interrupt does not check for interrupt enable flag is at logic 1, i.e, NMI is not maskable internally by software. If NMI is activated, the interrupt input uses interrupt vector 2.

RESET : The reset input causes the microprocessor to reset itself. When 8086 reset, it restarts the execution from memory location FFFF0H . The reset signal is active high and must be active for at least four clock cycles.

CLK : Clock input: The clock input signal provides the basic timing input signal for processor and bus control operation. It is asymmetric square wave with 33% duty cycle.

VCC power supply for the operation of the internal circuit

GND:Ground for the internal circuit

: The minimum/maximum mode signal to select the mode of operation either in minimum or maximum mode configuration. Logic 1 indicates minimum mode.