Organization of Intel 8085 Microprocessors                                                                                                  Print this page
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S0 and S1 : The status of the system bus is difined by the S0 and S1 lines as follows -

S1

S0

Operation Specified

0

0

Halt

0

1

Memory or I/O WRITE

1

0

Memory or I/O READ

1

1

Instruction Fetch

There are ten lines associated with CPU and bus control-

  • TRAP , RST7.5 , RST6.5 , RST5.5 and INTR are the Interrupt lines.
  • INTA: Interrupt acknowledge line.
  • RESET IN : This is the reset input signal to the 8085.
  • RESET OUT : The 8085 generates the RESET-OUT signal in response to RESET-IN signal , which can be used as a system reset signal .
  • HOLD : HOLD signal is used for DMA request.
  • HLDA : HLDA signal is used for DMA grant .

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