• By the end of the second clock cycle, the execution of the instruction is completed and instruction is available.


• Instruction is stored in buffer replacing ,  which is no longer needed.


• Step is performed by the execution unit during the third clock cycle, while instruction is being fetched by the fetch unit.


• Both the fetch and execute units are kept busy all the time and one instruction is completed after each clock cycle except the first clock cycle.


• If a long sequence of instructions is executed, the completion rate of instruction execution will be twice that achievable by the sequential operation with only one unit that performs both fetch and execute.

Basic idea of instruction pipelining with hardware organization is shown in the Figure 9.2.