Pipelining                                                                                                                         Print this page
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Now consider a CPU that has two separate hardware units, one for fetching instructions and another for executing them.

The instruction fetch by the fetch unit is stored in an intermediate storage buffer

The results of execution are stored in the destination location specified by the instruction.

For simplicity it is assumed that fetch and execute steps of any instruction can be completed in one clock cycle.

The operation of the computer proceeds as follows:

  • In the first clock cycle, the fetch unit fetches an instruction (instruction , step ) and stored it in buffer   at the end of the clock cycle.

  • In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for instruction (step ).

  • Meanwhile, the execution unit performs the operation specified by instruction which is already fetched and available in the buffer (step ).
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