By looking into the above three instructions, we can write the logic function for  Z_in  as :

                      Z_in =   T₁   +    T₆ . ADD_MD     +     T₅ . BR +    T₅ . BRN +  . . . . . . . . . . . . . .

For all instructions, in time step1 we need the control signal Z_in  to enable the input to register Z_in  time cycle T₆ of ADD_MD instruction, in time cycle T₅  of BR  instruction and so on.

Similarly,   the Boolean logic function for ADD signal is

                      ADD   =  T₁  +   T₆ . ADD_MD  +   T₅ . BR  +  . . . . . . . . . . . . . .

These logic functions can be implemented by a two level combinational circuit of  AND  and  OR  gates.

Similarly, the END control signal is generated by the logic function :

                      END   = T₈. ADD_MD    +    T₇ . BR   +   (  T₇ . N   +   T₄ . ) . BRN  +  . . . . . . . . . . . . . .

This END signal indicates the end of the execution of an instruction, so this END signal can be used to start a new instruction fetch cycle by resetting the control step counter to its starting value.