All input signals to the encoder block should be combined to generate the individual control signals.

In the previous section, we have mentioned the control sequence of the instruction,

"Add contents of memory location address in memory direct made to register R₁  ( ADD_MD)",

"Control sequence for an unconditional branch instruction (BR)",

also,  we have mentioned about Branch on negative (BRN).

Consder those three CPU instruction ADD_MD,   BR,   BRN.

It is required to generate many control signals by the control unit. These are basically coming out from the encoder circuit of the control signal generator.  The control signals are: PC_in, PC_out,  Z_in, Z_out, MAR_in, ADD, END, etc.