Every virtual memory reference can cause two physical memory accesses.
One to fetch the appropriate page table entry
One to fetch the desired data.
Thus a straight forward virtual memory scheme would have the effect of doubling the memory access time.
To overcome this problem, most virtual memory schemes make use of a special cache for page table entries, usually called Translation Lookaside Buffer (TLB).
This cache functions in the same way as a memory cache and contains those page table entries that have been most recently used.
In addition to the information that constitutes a page table entry, the TLB must also include the virtual address of the entry.
The Figure 3.27 shows a possible organization of a TLB whwere the associative mapping technique is used.