The memory control circuitry is designed to take advantage of the property of locality of reference. Some assumptions are made while designing the memory control circuitry:
- The CPU does not need to know explicitly about the existence of the cache.
- The CPU simply makes Read and Write request. The nature of these two operations are same whether cache is present or not.
- The address generated by the CPU always refer to location of main memory.
- The memory access control circuitry determines whether or not the requested word currently exists in the cache.
When a Read request is received from the CPU, the contents of a block of memory words containing the location specified are transferred into the cache. When any of the locations in this block is referenced by the program, its contents are read directly from the cache.
Consider the case where the addressed word is not in the cache and the operation is a read. First the block of words is brought to the cache and then the requested word is forwarded to the CPU. But it can be forwarded to the CPU as soon as it is available to the cache, instaead of the whole block to be loaded in the cache. This is called load through, and there is some scope to save time while using load through policy.
The cache memory can store a number of such blocks at any given time.
The correspondence between the Main Memory Blocks and those in the cache is specified by means of a mapping function.