Course abstract

This is a most fundamental Digital Circuit Design course for pursing a major in VLSI. We do not deal with any Verilog coding during this course and instead discuss transistor level circuit design concepts in great detail. Over learning objectives of this course are: 1. Characterize the key delay quantities of a standard cell 2. Evaluate power dissipated in a circuit (dynamic and leakage) 3. Design a circuit to perform a certain functionality with specified speed 4. Identify the critical path of a combinational circuit 5. Convert the combinational block to pipelined circuit 6. Calculate the maximum (worst case) operating frequency of the designed circuit