Course Name: Optimization Techniques for Digital VLSI Design

Course abstract

Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. This course will give a brief overview of the VLSI design flow. The primary emphasis of the course is to introduce the important optimization techniques applied in the Industry level electronic design automation (EDA) tools in the VLSI design flow. This course is unique in the sense that it will give a comprehensive idea about the widely used optimization techniques and their impact the generated hardware. The outline of the course is as follows: VLSI Design: Overview of digital VLSI design flow; High-level Synthesis, logic synthesis and physical synthesis and optimization techniques applied in these three steps; Impact of compiler optimization on hardware synthesis, 2-level logic optimization, multi-level logic optimizations, ESPRESSO; Technology Mapping: DSP and RAM inference for FPGA. RTL Optimizations: Area, power and timing optimization techniques like retiming, register balancing, folding. pipelining, and clock gating. VLSI Test: Introduction to Automatic Test Pattern Generation (ATPG), optimization Techniques for ATPG, design for Testability, optimization Techniques for design for testability, High-level fault modeling, RTL level Testing Verification: LTL and CTL based hardware verification, verification of large systems, binary decision diagram (BDD) based verification, arithmetic decision diagram based (ADD) and high-level decision diagram (HDD) based verification, symbolic model checking, bounded model checking.


Course Instructor

Media Object

Prof. Chandan Karfa_x000D_

Dr. Chandan Karfa is an Assistant Professor in the Dept. of CSE, IIT Guwahati. He has worked for five years as Senior R&D engineer in EDA Industry. He has also one and half years of teaching experience. His research interests include High-level Synthesis, CAD for VLSI and Formal Verification.


Teaching Assistant(s)

Surajit Das

Persuing PhD, Computer Science and Engineering

Sanjit Kumar Roy

PhD, Dept. of Computer Science & Engineering

 Course Duration : Feb-Mar 2018

  View Course

 Syllabus

 Enrollment : 20-Nov-2017 to 05-Feb-2018

 Exam registration : 08-Jan-2018 to 07-Mar-2018

 Exam Date : 28-Apr-2018, 29-Apr-2018

Enrolled

2602

Registered

80

Certificate Eligible

60

Certified Category Count

Gold

1

Elite

19

Successfully completed

40

Participation

11

Success

Elite

Gold





Legend

>=90 - Elite + Gold
60-89 - Elite
40-59 - Successfully Completed
<40 - No Certificate

Final Score Calculation Logic

  • Assignment Score = Average of best 6 out of 8 assignments.
  • Final Score(Score on Certificate)= 75% of Exam Score + 25% of Assignment Score
Optimization Techniques for Digital VLSI Design - Toppers list

RASHMI RAVINATHAN 90%

NA

PAMPANA NAGARJUNA 87%

BML MUNJAL UNIVERSITY

RAJ SHINGALA 86%

DHARAMSINH DESAI UNIVERSITY,NADIAD

ANANTVIJAY S. SOLANKI 83%

SELF

JAYATIKA SAKHUJA 81%

SAMTEL AVIONICS

Enrollment Statistics

Total Enrollment: 2602

Registration Statistics

Total Registration : 80

Assignment Statistics




Assignment

Exam score

Final score

Score Distribution Graph - Legend

Assignment Score: Distribution of average scores garnered by students per assignment.
Exam Score : Distribution of the final exam score of students.
Final Score : Distribution of the combined score of assignments and final exam, based on the score logic.