Course Name: Hardware modeling using verilog

Course abstract

The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.


Course Instructor

Media Object

Prof. Indranil Sengupta

Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of Computer Science and Engineering, where he is presently a full Professor. He had been the former Heads of the Department of Computer Science and Engineering and also the School of Information Technology of the Institute. He has over 28 years of teaching and research experience. He has guided 22 PhD students, and has more than 200 publications to his credit in international journals and conferences. His research interests include cryptography and network security, VLSI design and testing, and mobile computing. He is a Senior Member of IEEE. He had been the General Chairs of Asian Test Symposium (ATS-2005), International Conference on Cryptology in India (INDOCRYPT-2008), International Symposium on VLSI Design and Test (VDAT-2012), International Symposium on Electronic System Design (ISED-2012), and the upcoming Conference on reversible Computation (RC-2017). He had delivered invited and tutorial talks in several conferences in the areas of VLSI design and testing, network security, and side-channel attacks on cryptographic implementations.


More info

Teaching Assistant(s)

DR. KAMALIKA DATTA

PhD, Information Technology, IIEST Shibpur

Abhoy Kole

M.Tech., Information and Communication Technology
IIT Kharagpur

 Course Duration : Aug-Oct 2017

  View Course

 Syllabus

 Enrollment : 17-May-2017 to 21-Aug-2017

 Exam registration : 30-Aug-2017 to 20-Sep-2017

 Exam Date : 22-Oct-2017

Enrolled

5847

Registered

Certificate Eligible

260

Certified Category Count

Gold

5

Elite

116

Successfully completed

139

Participation

155

Success

Elite

Gold





Legend

>=90 - Elite + Gold
60-89 - Elite
40-59 - Successfully Completed
<40 - No Certificate

Final Score Calculation Logic

  • Assignment Score = Average of best 6 out of 8 assignments.
  • Final Score(Score on Certificate)= 75% of Exam Score + 25% of Assignment Score.
  • NOTE:For weeks that had multiple assignments, the average of scores of all assignments has been considered as score for that week. Best 6 out of 8 such assignment scores has been considered.
Hardware modeling using verilog - Toppers list
Top 1 % of Certified Candidates

ALFRED FESTUS DAVIDSON 94%

INDIAN INSTITUTE OF TECHNOLOGY MADRAS

K JAYADITYA NARAYANA 93%

AMRITA SCHOOL OF ENGINEERING AMRITA UNIVERSITY

SREEKANTH REDDY BODEDDULA 93%

G. NARAYANAMMA INSTITUTE OF TECHNOLOGY AND SCIENCE (FOR WOMEN)


Top 2 % of Certified Candidates

VIKRANT RATHOD 91%

DELHI TECHNOLOGICAL UNIVERSITY

DEEPANK GROVER 90%

DELHI TECHNOLOGICAL UNIVERSITY


Top 5 % of Certified Candidates

AKSHAY TANEJA 89%

ANSYS

NARENDIRAN 88%

PONDICHERRY ENGINEERING COLLEGE

KARTHIK VIVEK NAYAK 87%

GOGTE INSTITUTE OF TECHNOLOGY

KONDA LAKSHMIKANTHGARI NAVEEN KUMAR 86%

NIT NAGALAND

PRITI RATHI 86%

NATIONAL INSTITUTE OF TECHNOLOGY

SEEMA S 86%

MANIPAL INSTITUTE OF TECHNOLOGY MANIPAL

TRIBHUVAN L 86%

BMS COLLEGE OF ENGINEERING

RAJ SHINGALA 83%

DHARAMSINH DESAI UNIVERSITY,NADIAD

DR. P. SARAVANAN 83%

PSG COLLEGE OF TECHNOLOGY

SHANTHI REKHA S 83%

PSG COLLEGE OF TECHNOLOGY

HONEY GAHLAWAT 83%

CADENCE DESIGN SYSTEMS LTD

SHIVAM JAISWAL 83%

MANIPAL UNIVERSITY JAIPUR

LAKSHMI H R 83%

K S INSTITUTE OF TECHNOLOGY

Enrollment Statistics

Total Enrollment: 5847

Registration Statistics

Total Registration : 515

Data Not Found..!

Assignment Statistics




Assignment

Exam score

Final score

Score Distribution Graph - Legend

Assignment Score: Distribution of average scores garnered by students per assignment.
Exam Score : Distribution of the final exam score of students.
Final Score : Distribution of the combined score of assignments and final exam, based on the score logic.