| Name | Download | Download Size |
|---|---|---|
| Lecture Note | Download as zip file | 33M |
| Module Name | Download | Description | Download Size |
|---|---|---|---|
| Week 1 | Module 3 | Hand notes | 392 |
| Week 1 | Module 5 | Hand notes | 163 |
| Week 2 | Module 9 | Hand notes | 427 |
| Week 2 | Module10-12 | Hand notes | 441 |
| Week 3 | Module 15 | Hand notes | 92 |
| Week 3 | Module 17 | Hand notes | 92 |
| Week 4 | Module 21 | Hand notes | 214 |
| Week 5 | Module 23 | Hand notes | 80 |
| Week 5 | Module 27 | Hand notes | 435 |
| Week 6 | Module 30 | Hand notes | 325 |
| Week 6 | Module 34 | Hand notes | 102 |
| Week 7 | Week 7 | Hand notes | 849 |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction | Download To be verified |
| 2 | Basic Boolean Logic | Download To be verified |
| 3 | Boolean Theorems | Download To be verified |
| 4 | Definitions, SoP and Pos | Download To be verified |
| 5 | Algebraic Minimization Examples | Download To be verified |
| 6 | Introduction to Verilog | Download To be verified |
| 7 | Universality, Rearranging Truth Tables | Download To be verified |
| 8 | Karnaugh Maps | Download To be verified |
| 9 | K-Map Minimization | Download To be verified |
| 10 | K-Map with Don't cares | Download To be verified |
| 11 | Multiple Output Functions | Download To be verified |
| 12 | Number Systems | Download To be verified |
| 13 | Encoders and Decoders | Download To be verified |
| 14 | Multiplexers | Download To be verified |
| 15 | Multiplexer based Circuit Design | Download To be verified |
| 16 | Verilog | Download To be verified |
| 17 | Compiling and Running Verilog - A Demonstration | Download To be verified |
| 18 | Sequential Elements | Download To be verified |
| 19 | Gated Latches | Download To be verified |
| 20 | Flipflops | Download To be verified |
| 21 | Verilog - Assign Statement and Instantiation | Download To be verified |
| 22 | Sequential Circuits | Download To be verified |
| 23 | CMOS+Electrical Properties | Download To be verified |
| 24 | Delays | Download To be verified |
| 25 | Sequential Element Delays | Download To be verified |
| 26 | More Sequential Circuits | Download To be verified |
| 27 | Introduction to State Machines | Download To be verified |
| 28 | Always Statement in Verilog | Download To be verified |
| 29 | Sequential Logic Synthesis | Download To be verified |
| 30 | FSM Design Problems | Download To be verified |
| 31 | State Minimization | Download To be verified |
| 32 | State Assignment | Download To be verified |
| 33 | Timing Sequential Circuits | Download To be verified |
| 34 | Verilog Styles + Sequential Elements | Download To be verified |
| 35 | GCD Algorithm | Download To be verified |
| 36 | GCD Machines Datapath | Download To be verified |
| 37 | GCD State Machine | Download To be verified |
| 38 | GCD Top Level Module | Download To be verified |
| 39 | Datapath in Verilog | Download To be verified |
| 40 | Datapath Elements in Verilog | Download To be verified |
| 41 | FSM in Verilog | Download To be verified |
| 42 | Putting it all together | Download To be verified |
| 43 | Pipelining | Download To be verified |
| 44 | K-stage Pipeline | Download To be verified |
| 45 | Interleaving and Parallelism | Download To be verified |
| 46 | Blocking and Non-blocking Statements | Download To be verified |
| 47 | Modeling Circuits with Pipelining | Download To be verified |
| 48 | Signed Number Representation | Download To be verified |
| 49 | Signed Number Addition | Download To be verified |
| 50 | Adder/Subtracter | Download To be verified |
| 51 | Fast Adders | Download To be verified |
| 52 | Multiplication | Download To be verified |
| 53 | Closing Remarks | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |