| 1 | MOS Transistor | PDF unavailable |
| 2 | MOS Transistor - Detailed Study | PDF unavailable |
| 3 | Combinational Circuits & layout | PDF unavailable |
| 4 | Delay | PDF unavailable |
| 5 | Sequential Circuits | PDF unavailable |
| 6 | Logical Effort | PDF unavailable |
| 7 | Circuit Families | PDF unavailable |
| 8 | Lab-01 | PDF unavailable |
| 9 | Lab-02 | PDF unavailable |
| 10 | Lab-03 | PDF unavailable |
| 11 | Lab-04 | PDF unavailable |
| 12 | Introduction to Synthesis | PDF unavailable |
| 13 | Libraries | PDF unavailable |
| 14 | RTL Coding for Synthesis | PDF unavailable |
| 15 | Reading Design in DC | PDF unavailable |
| 16 | Design Environment | PDF unavailable |
| 17 | Design Constraints | PDF unavailable |
| 18 | Compile Flow and stratergies | PDF unavailable |
| 19 | Analysis and Reporting | PDF unavailable |
| 20 | Lab-05 | PDF unavailable |
| 21 | Advanced Synthesis Techniques | PDF unavailable |
| 22 | Datapath Extraction Guidelines | PDF unavailable |
| 23 | Power - Methodology and Analysis | PDF unavailable |
| 24 | Lab-06 | PDF unavailable |
| 25 | Lab-07 | PDF unavailable |
| 26 | Lab-08 | PDF unavailable |
| 27 | Lab-09 | PDF unavailable |
| 28 | Static Timing Analysis - Concepts and Flow | PDF unavailable |
| 29 | Interconnects and Delay calculation | PDF unavailable |
| 30 | Clock and Exceptions | PDF unavailable |
| 31 | On Chip Variation | PDF unavailable |
| 32 | Introduction to Crosstalk | PDF unavailable |
| 33 | Gaussian / Normal Distribution | PDF unavailable |
| 34 | Equivalence Checking / Formal Verification | PDF unavailable |