| 1 | Introduction to Data Conversion | PDF unavailable |
| 2 | Sampling-1 | PDF unavailable |
| 3 | Sampling-2 | PDF unavailable |
| 4 | Nonidealities in Samples | PDF unavailable |
| 5 | Noise due to Sampling | PDF unavailable |
| 6 | Distortion in a Sampling Switch | PDF unavailable |
| 7 | Gate Boosted Switches-1 | PDF unavailable |
| 8 | Gate Boosted Switches-2 | PDF unavailable |
| 9 | Charge Injection | PDF unavailable |
| 10 | S/H Characterization-1 | PDF unavailable |
| 11 | S/H Characterization-2 | PDF unavailable |
| 12 | FFTs and Leakage | PDF unavailable |
| 13 | Spectral Windows-1 | PDF unavailable |
| 14 | Spectral Windows-2 | PDF unavailable |
| 15 | ADC/DAC Definition | PDF unavailable |
| 16 | Quantization Noise-1 | PDF unavailable |
| 17 | Quantization Noise-2 | PDF unavailable |
| 18 | Over Sampling and Noise Shaping | PDF unavailable |
| 19 | Delta-Sigma Modulation-1 | PDF unavailable |
| 20 | Delta-Sigma Modulation-2 | PDF unavailable |
| 21 | Linearized Analysis | PDF unavailable |
| 22 | Stability of Delta Sigma Modulators | PDF unavailable |
| 23 | High Order DSMs | PDF unavailable |
| 24 | NTF Design and Tradeoffs | PDF unavailable |
| 25 | Single bit Modulators | PDF unavailable |
| 26 | Loop Filter Architectures | PDF unavailable |
| 27 | Continous-time Delta Sigma Modulation | PDF unavailable |
| 28 | Implicit Antialiasing | PDF unavailable |
| 29 | Modulators with NRZ and Impulsive DACs | PDF unavailable |
| 30 | High Order CTDSMs | PDF unavailable |
| 31 | CTDM Design | PDF unavailable |
| 32 | Excess Loop Delay (ELD) | PDF unavailable |
| 33 | ELD Compensation | PDF unavailable |
| 34 | Effect of Clock Jitter on CTDSMs-1 | PDF unavailable |
| 35 | Effect of Clock Jitter on CTDSMs-2 | PDF unavailable |
| 36 | Dynamic Range Scaling | PDF unavailable |
| 37 | Simulation of CTDSMs | PDF unavailable |
| 38 | Integrator Design-1 | PDF unavailable |
| 39 | Integrator Design-2 | PDF unavailable |
| 40 | Flash ADC Design | PDF unavailable |
| 41 | Latches and Metastability | PDF unavailable |
| 42 | Offset in a Latch-1 | PDF unavailable |
| 43 | Offset in a Latch-2 Auto Zeroing | PDF unavailable |
| 44 | Auto Zeroing-2 | PDF unavailable |
| 45 | Auto Zeroing-3 | PDF unavailable |
| 46 | Auto Zeroing in flash ADCs | PDF unavailable |
| 47 | Flash ADCs Case Study | PDF unavailable |
| 48 | Flash ADC Case Study | PDF unavailable |
| 49 | Flash ADC in a Delta Sigma Loop | PDF unavailable |
| 50 | DAC Basics | PDF unavailable |
| 51 | Binary and Themometer DACs | PDF unavailable |
| 52 | Segmented DACs | PDF unavailable |
| 53 | Optimal DAC Segmentation | PDF unavailable |
| 54 | DAC Nonlinearities | PDF unavailable |
| 55 | Current Steering DACs-1 | PDF unavailable |
| 56 | Current Steering DACs-2 | PDF unavailable |
| 57 | DAC Mismatches in DSMs | PDF unavailable |
| 58 | Calibration and Randomization | PDF unavailable |
| 59 | Dynamic Element Matching-1 | PDF unavailable |
| 60 | Dynamic Element Matching-2 | PDF unavailable |