| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Course Introduction and Motivation Part I | Download Verified |
| 2 | Course Introduction and Motivation Part II | Download Verified |
| 3 | Basic Operation of a Phase Locked Loop | Download Verified |
| 4 | Simple Implementation of a Phase Locked Loop | Download Verified |
| 5 | Input Output Characteristics of Basic PLL Blocks | Download Verified |
| 6 | Time Domain Analysis of a Simple PLL | Download Verified |
| 7 | Time Domain Versus Small Signal Analysis of a Simple PLL | Download Verified |
| 8 | Type and Order of PLL | Download Verified |
| 9 | Small Signal Analysis of Type-I/II/III PLLs for Phase Step, Frequency Step and Frequency Ramp | Download Verified |
| 10 | Frequency Acquisition Range for PLLs | Download Verified |
| 11 | Frequency Acquisition in Type-I PLLs | Download Verified |
| 12 | Frequency Acquisition Limits in Type-I PLLs | Download Verified |
| 13 | Frequency Acquisition in Type II PLLs | Download Verified |
| 14 | Frequency Acquisition Ranges in Type II PLLs with Ideal and Non Ideal Integrator | Download Verified |
| 15 | Frequency Domain Insight in Frequency Acquisition for Type II PLLs | Download Verified |
| 16 | Introduction to Clock Multipliers | Download Verified |
| 17 | Analog Phase Error Detectors: Part I | Download Verified |
| 18 | Analog Phase Error Detectors: Part II | Download Verified |
| 19 | Digital Phase Error Detectors: Part I | Download Verified |
| 20 | Digital Phase Error Detectors: Part II | Download Verified |
| 21 | Range Extension for Phase Error Detectors | Download Verified |
| 22 | Phase Frequency Detector | Download Verified |
| 23 | Digital Frequency Detector | Download Verified |
| 24 | Charge Pump PLL | Download Verified |
| 25 | Small Signal and Stability Analysis of Type II Order 2 Charge Pump PLL | Download Verified |
| 26 | Problems in Charge Pump PLL - Dead Zone in PFD | Download Verified |
| 27 | Problems in Charge Pump PLL - Reference Spur | Download Verified |
| 28 | Design Procedure for Type-II Order 3 Charge Pump PLL | Download Verified |
| 29 | Design Procedure for Charge Pump Clock Multiplier | Download Verified |
| 30 | Sources of Non-Linearities in CP-PLL: Part I | Download Verified |
| 31 | Sources of Non-Linearities in CP-PLL: Part II | Download Verified |
| 32 | Noise Analysis in CP-PLL: Part I | Download Verified |
| 33 | Noise Analysis in CP PLL: Part II | Download Verified |
| 34 | Noise Analysis in CP-PLL: Part III | Download Verified |
| 35 | Noise Simulations for CP-PLL Blocks | Download Verified |
| 36 | Introduction to Oscillators | Download Verified |
| 37 | Low Swing Ring Oscillator: Part I | Download Verified |
| 38 | Low-Swing Ring Oscillator: Part II | Download Verified |
| 39 | Large-Swing Ring Oscillator: Part I | Download Verified |
| 40 | Large-Swing Ring Oscillator: Part II | Download Verified |
| 41 | Large-Swing Ring Oscillator: Part III | Download Verified |
| 42 | Large-Swing Ring Oscillator: Part IV | Download Verified |
| 43 | Large-Swing Ring Oscillator: Part V | Download Verified |
| 44 | Supply Regulated VCO: Part I | Download Verified |
| 45 | Supply Regulated VCO: Part II | Download Verified |
| 46 | Supply Regulated VCO: Part III | Download Verified |
| 47 | Phase Noise in Ring Oscillators | Download Verified |
| 48 | Circuit level Design of PFD: Part I | Download Verified |
| 49 | Circuit level Design of PFD: Part II | Download Verified |
| 50 | Circuit level Design of PFD: Part III | Download Verified |
| 51 | Circuit level Design of Charge Pump: Part I | Download Verified |
| 52 | Circuit-level Design of Charge Pump: Part II | Download Verified |
| 53 | Circuit-level Design of Charge Pump: Part III | Download Verified |
| 54 | Circuit-level Design of Charge Pump: Part IV | Download Verified |
| 55 | Circuit-level Design of Charge Pump: Part V | Download Verified |
| 56 | Circuit-level Design of Charge Pump: Part VI | Download Verified |
| 57 | Circuit-level Design of Clock Frequency Divider | Download Verified |
| 58 | Techniques for Wide Frequency Range Clock Multiplier | Download Verified |
| 59 | Introduction to Digital PLL | Download Verified |
| 60 | Design of Time-to-Digital Converter | Download Verified |
| 61 | Small Signal Analysis of Digital PLL | Download Verified |
| 62 | Noise Analysis in Digital PLL | PDF unavailable |
| 63 | Analog/Digital Hybrid PLL: Part I | PDF unavailable |
| 64 | Analog/Digital Hybrid PLL: Part II | PDF unavailable |
| 65 | Course Summary | PDF unavailable |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |