Toggle navigation
About us
Courses
Contact us
Courses
Computer Science and Engineering
CAD for VLSI Design I (Web)
Syllabus
Co-ordinated by :
IIT Madras
Available from :
2009-12-31
Lec :
1
Modules / Lectures
CAD for VLSI Design I
Evolution of CAD Tools
Importance of Design Automation
Basic Transistor Fundamentals
Gate Level Modeling
Higher Levels of Modeling
Types of CAD Tools
Verilog Quick Starter
Introduction to Simulators
Verilog Syntax
Verilog - Operators and expressions
Hierarchical Design and methodology
Delay modeling
Delay Modeling (contd)
Blocking and Non Blocking Assignments
Behavioural Modeling
Verilog Tasks and Functions
Memory Modeling
Advanced Delay Modeling
Advanced Delay Modeling (Contd)
Verilog Tricks
Introduction to Logic Synthesis
Logic Synthesis (Contd)
Logic Synthesis (Contd)
Synthesis: Assignment Statements
Synthesis: Arithmetic Operators
Synthesis: Bit Selects
Synthesis: Conditional Statements
Synthesis: Case Statements
Synthesis: Case Statements (Contd)
Synthesis: Loops
Synthesis: Local & Integer Variables
Synthesis: Flip Flops with preset / clear
Synthesis: Blocking Vs Non Blocking Assignments
Synthesis: Unknowns and High Impedance
Optimization in Synthesis
Optimization in Synthesis (Contd)
Introduction to Reconfigurable Computing
Introduction to FPGAs
Introduction to FPGAs (Contd)
The Altera Quartus Flow
Web Content
Downloads
loading...