| Name | Download | Download Size |
|---|---|---|
| Lecture Note | Download as zip file | 77M |
| Module Name | Download |
|---|---|
| noc19_cs03_Assignment1 | noc19_cs03_Assignment1 |
| noc19_cs03_Assignment10 | noc19_cs03_Assignment10 |
| noc19_cs03_Assignment11 | noc19_cs03_Assignment11 |
| noc19_cs03_Assignment12 | noc19_cs03_Assignment12 |
| noc19_cs03_Assignment2 | noc19_cs03_Assignment2 |
| noc19_cs03_Assignment3 | noc19_cs03_Assignment3 |
| noc19_cs03_Assignment4 | noc19_cs03_Assignment4 |
| noc19_cs03_Assignment5 | noc19_cs03_Assignment5 |
| noc19_cs03_Assignment6 | noc19_cs03_Assignment6 |
| noc19_cs03_Assignment7 | noc19_cs03_Assignment7 |
| noc19_cs03_Assignment8 | noc19_cs03_Assignment8 |
| noc19_cs03_Assignment9 | noc19_cs03_Assignment9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Lecture 1 : Evolution of Computer Systems | Download |
| 2 | Lecture 2 : Basic Operation of a Computer | Download |
| 3 | Lecture 3 : Memory Addressing and Languages | Download |
| 4 | Lecture 4 : Software and Architecture Types | Download |
| 5 | Lecture 5 : Instruction Set Architecture | Download |
| 6 | Lecture 6 : Number Representation | Download |
| 7 | Lecture 7 : Instruction Format and Addressing Modes | Download |
| 8 | Lecture 8 : CISC and RISC Architecture | Download |
| 9 | Lecture 9 : MIPS32 Instruction Set | Download |
| 10 | Lecture 10 MIPS Programming Examples | Download |
| 11 | Lecture 11 : SPIM – A MIPS32 SIMULATOR | Download |
| 12 | Lecture 12 : MEASURING CPU PERFORMANCE | Download |
| 13 | Lecture 13 : CHOICE OF BENCHMARKS | Download |
| 14 | Lecture 14 : SUMMARIZING PERFORMANCE RESULTS | Download |
| 15 | Lecture 15 : AMADAHL’S LAW (PART 1) | Download |
| 16 | Lecture 16 : AMADAHL’S LAW (PART 2) | Download |
| 17 | Lecture 17 : DESIGN OF CONTROL UNIT (PART 1) | Download |
| 18 | Lecture 18 :DESIGN OF CONTROL UNIT (PART 2) | Download |
| 19 | Lecture 19 : DESIGN OF CONTROL UNIT (PART 3) | Download |
| 20 | Lecture 20 : DESIGN OF CONTROL UNIT (PART 4) | Download |
| 21 | Lecture 21 : MIPS IMPLEMENTATION (PART 1) | Download |
| 22 | Lecture 22 : MIPS IMPLEMENTATION (PART 2) | Download |
| 23 | Lecture 23 : PROCESSOR MEMORY INTERACTION | Download |
| 24 | Lecture 24 : STATIC AND DYNAMIC RAM | Download |
| 25 | Lecture 25 : ASYNCHRONOUS DRAM | Download |
| 26 | Lecture 26 : SYNCHRONOUS DRAM | Download |
| 27 | Lecture 27 :MEMORY INTERFACING AND ADDRESSING | Download |
| 28 | Lecture 28 : MEMORY HIERARCHY DESIGN (PART 1) | Download |
| 29 | Lecture 29 : MEMORY HIERARCHY DESIGN (PART 2) | Download |
| 30 | Lecture 30 : CACHE MEMORY (PART 1) | Download |
| 31 | Lecture 31 : CACHE MEMORY (PART 2) | Download |
| 32 | Lecture 32 : IMPROVING CACHE PERFORMANCE | Download |
| 33 | Lecture 33 : DESIGN OF ADDERS (PART 1) | Download |
| 34 | Lecture 34 : DESIGN OF ADDERS (PART 2) | Download |
| 35 | Lecture 35 : DESIGN OF MULTIPLIERS (PART 1) | Download |
| 36 | Lecture 36 : DESIGN OF MULTIPLIERS (PART 2) | Download |
| 37 | Lecture 37 : DESIGN OF DIVIDERS | Download |
| 38 | Lecture 38 : FLOATING-POINT NUMBERS | Download |
| 39 | Lecture 39 : FLOATING-POINT ARITHMETIC | Download |
| 40 | Lecture 40 : BASIC PIPELINING CONCEPTS | Download |
| 41 | Lecture 41 : PIPELINE SCHEDULING | Download |
| 42 | Lecture 42 : ARITHMETIC PIPELINE | Download |
| 43 | Lecture 43 : SECONDARY STORAGE DEVICES | Download |
| 44 | Lecture 44 : INPUT-OUTPUT ORGANIZATION | Download |
| 45 | Lecture 45 : DATA TRANSFER TECHNIQUES | Download |
| 46 | Lecture 46 : INTERRUPT HANDLING (PART 1) | Download |
| 47 | Lecture 47 : INTERRUPT HANDLING (PART 2) | Download |
| 48 | Lecture 48 : DIRECT MEMORY ACCESS | Download |
| 49 | Lecture 49 : SOME EXAMPLE DEVICE INTERFACING | Download |
| 50 | Lecture 50: EXERCISES ON I/O TRANSFER | Download |
| 51 | Lecture 51 : BUS STANDARDS | Download |
| 52 | Lecture 52 : BUS STANDARDS | Download |
| 53 | Lecture 53: PIPELINING THE MIPS32 DATA PATH | Download |
| 54 | Lecture 54: MIPS PIPELINE (Contd.) | Download |
| 55 | Lecture 55: PIPELINE HAZARDS (PART 1) | Download |
| 56 | Lecture 56: PIPELINE HAZARDS (PART 2) | Download |
| 57 | Lecture 57: PIPELINE HAZARDS (PART 3) | Download |
| 58 | Lecture 58: PIPELINE HAZARDS (PART 4) | Download |
| 59 | Lecture 59 : MULTICYCLE OPERATIONS IN MIPS32 | Download |
| 60 | Lecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISM | Download |
| 61 | Lecture 61 : VECTOR PROCESSORS | Download |
| 62 | Lecture 62: MULTI-CORE PROCESSORS | Download |
| 63 | Lecture 63 : SOME CASE STUDIES | Download |
| 64 | Lecture 64 : SUMMARIZATION OF THE COURSE | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Lecture 1 : Evolution of Computer Systems | Download Verified |
| 2 | Lecture 2 : Basic Operation of a Computer | Download Verified |
| 3 | Lecture 3 : Memory Addressing and Languages | Download Verified |
| 4 | Lecture 4 : Software and Architecture Types | Download Verified |
| 5 | Lecture 5 : Instruction Set Architecture | Download Verified |
| 6 | Lecture 6 : Number Representation | Download Verified |
| 7 | Lecture 7 : Instruction Format and Addressing Modes | Download Verified |
| 8 | Lecture 8 : CISC and RISC Architecture | Download Verified |
| 9 | Lecture 9 : MIPS32 Instruction Set | Download Verified |
| 10 | Lecture 10 MIPS Programming Examples | Download Verified |
| 11 | Lecture 11 : SPIM – A MIPS32 SIMULATOR | Download Verified |
| 12 | Lecture 12 : MEASURING CPU PERFORMANCE | Download Verified |
| 13 | Lecture 13 : CHOICE OF BENCHMARKS | Download Verified |
| 14 | Lecture 14 : SUMMARIZING PERFORMANCE RESULTS | Download Verified |
| 15 | Lecture 15 : AMADAHL’S LAW (PART 1) | Download Verified |
| 16 | Lecture 16 : AMADAHL’S LAW (PART 2) | Download Verified |
| 17 | Lecture 17 : DESIGN OF CONTROL UNIT (PART 1) | Download Verified |
| 18 | Lecture 18 :DESIGN OF CONTROL UNIT (PART 2) | Download Verified |
| 19 | Lecture 19 : DESIGN OF CONTROL UNIT (PART 3) | Download Verified |
| 20 | Lecture 20 : DESIGN OF CONTROL UNIT (PART 4) | Download Verified |
| 21 | Lecture 21 : MIPS IMPLEMENTATION (PART 1) | Download Verified |
| 22 | Lecture 22 : MIPS IMPLEMENTATION (PART 2) | Download Verified |
| 23 | Lecture 23 : PROCESSOR MEMORY INTERACTION | Download Verified |
| 24 | Lecture 24 : STATIC AND DYNAMIC RAM | Download Verified |
| 25 | Lecture 25 : ASYNCHRONOUS DRAM | Download Verified |
| 26 | Lecture 26 : SYNCHRONOUS DRAM | Download Verified |
| 27 | Lecture 27 :MEMORY INTERFACING AND ADDRESSING | Download Verified |
| 28 | Lecture 28 : MEMORY HIERARCHY DESIGN (PART 1) | Download Verified |
| 29 | Lecture 29 : MEMORY HIERARCHY DESIGN (PART 2) | Download Verified |
| 30 | Lecture 30 : CACHE MEMORY (PART 1) | Download Verified |
| 31 | Lecture 31 : CACHE MEMORY (PART 2) | Download Verified |
| 32 | Lecture 32 : IMPROVING CACHE PERFORMANCE | Download Verified |
| 33 | Lecture 33 : DESIGN OF ADDERS (PART 1) | Download Verified |
| 34 | Lecture 34 : DESIGN OF ADDERS (PART 2) | Download Verified |
| 35 | Lecture 35 : DESIGN OF MULTIPLIERS (PART 1) | Download Verified |
| 36 | Lecture 36 : DESIGN OF MULTIPLIERS (PART 2) | Download Verified |
| 37 | Lecture 37 : DESIGN OF DIVIDERS | Download Verified |
| 38 | Lecture 38 : FLOATING-POINT NUMBERS | Download Verified |
| 39 | Lecture 39 : FLOATING-POINT ARITHMETIC | Download Verified |
| 40 | Lecture 40 : BASIC PIPELINING CONCEPTS | Download Verified |
| 41 | Lecture 41 : PIPELINE SCHEDULING | Download Verified |
| 42 | Lecture 42 : ARITHMETIC PIPELINE | Download Verified |
| 43 | Lecture 43 : SECONDARY STORAGE DEVICES | Download Verified |
| 44 | Lecture 44 : INPUT-OUTPUT ORGANIZATION | Download Verified |
| 45 | Lecture 45 : DATA TRANSFER TECHNIQUES | Download Verified |
| 46 | Lecture 46 : INTERRUPT HANDLING (PART 1) | Download Verified |
| 47 | Lecture 47 : INTERRUPT HANDLING (PART 2) | Download Verified |
| 48 | Lecture 48 : DIRECT MEMORY ACCESS | Download Verified |
| 49 | Lecture 49 : SOME EXAMPLE DEVICE INTERFACING | Download Verified |
| 50 | Lecture 50: EXERCISES ON I/O TRANSFER | Download Verified |
| 51 | Lecture 51 : BUS STANDARDS | Download Verified |
| 52 | Lecture 52 : BUS STANDARDS | Download Verified |
| 53 | Lecture 53: PIPELINING THE MIPS32 DATA PATH | Download Verified |
| 54 | Lecture 54: MIPS PIPELINE (Contd.) | Download Verified |
| 55 | Lecture 55: PIPELINE HAZARDS (PART 1) | Download Verified |
| 56 | Lecture 56: PIPELINE HAZARDS (PART 2) | Download Verified |
| 57 | Lecture 57: PIPELINE HAZARDS (PART 3) | Download Verified |
| 58 | Lecture 58: PIPELINE HAZARDS (PART 4) | Download Verified |
| 59 | Lecture 59 : MULTICYCLE OPERATIONS IN MIPS32 | Download Verified |
| 60 | Lecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISM | Download Verified |
| 61 | Lecture 61 : VECTOR PROCESSORS | Download Verified |
| 62 | Lecture 62: MULTI-CORE PROCESSORS | Download Verified |
| 63 | Lecture 63 : SOME CASE STUDIES | Download Verified |
| 64 | Lecture 64 : SUMMARIZATION OF THE COURSE | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Download |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |