| Module Name | Download |
|---|---|
| noc20_cs18_assigment_1 | noc20_cs18_assigment_1 |
| noc20_cs18_assigment_10 | noc20_cs18_assigment_10 |
| noc20_cs18_assigment_11 | noc20_cs18_assigment_11 |
| noc20_cs18_assigment_12 | noc20_cs18_assigment_12 |
| noc20_cs18_assigment_13 | noc20_cs18_assigment_13 |
| noc20_cs18_assigment_2 | noc20_cs18_assigment_2 |
| noc20_cs18_assigment_3 | noc20_cs18_assigment_3 |
| noc20_cs18_assigment_4 | noc20_cs18_assigment_4 |
| noc20_cs18_assigment_5 | noc20_cs18_assigment_5 |
| noc20_cs18_assigment_6 | noc20_cs18_assigment_6 |
| noc20_cs18_assigment_7 | noc20_cs18_assigment_7 |
| noc20_cs18_assigment_8 | noc20_cs18_assigment_8 |
| noc20_cs18_assigment_9 | noc20_cs18_assigment_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Lecture 1: Introduction | Download Verified |
| 2 | Lecture 2: Design Representation | Download Verified |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download Verified |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download Verified |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download Verified |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download Verified |
| 7 | Lecture 7: Partitioning | Download Verified |
| 8 | Lecture 8: Floorplanning | Download Verified |
| 9 | Lecture 9: "Floorplanning Algorithms | Download Verified |
| 10 | Lecture 10: Pin Assignment | Download Verified |
| 11 | Lecture 11: Placement (Part 1) | Download Verified |
| 12 | Lecture 12: Placement (Part 2) | Download Verified |
| 13 | Lecture 13: Placement (Part 3) | Download Verified |
| 14 | Lecture 14: Placement (Part 4) | Download Verified |
| 15 | Lecture 15: Grid Routing (Part 1) | Download Verified |
| 16 | Lecture 16: Grid Routing (Part 2) | Download Verified |
| 17 | Lecture 17: Grid Routing (Part 3) | Download Verified |
| 18 | Lecture 18: Global Routing (Part 1) | Download Verified |
| 19 | Lecture 19: Global Routing (Part 2) | Download Verified |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download Verified |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download Verified |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download Verified |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download Verified |
| 24 | Lecture 24 : Clock Design (Part 1) | Download Verified |
| 25 | Lecture 25 : Clock Design (Part 2) | Download Verified |
| 26 | Lecture 26 : Clock Design (Part 3) | Download Verified |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download Verified |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download Verified |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download Verified |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download Verified |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download Verified |
| 32 | Lecture 32: Time Closure (Part 1) | Download Verified |
| 33 | Lecture 33: Time Closure (Part 2) | Download Verified |
| 34 | Lecture 34: Time Closure (Part 3) | Download Verified |
| 35 | Lecture 35: Time Closure (Part 4) | Download Verified |
| 36 | Lecture 36: Time Closure (Part 5) | Download Verified |
| 37 | Lecture 37: Timing Driven Placement | Download Verified |
| 38 | Lecture 38: Timing Driven Routing | Download Verified |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download Verified |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download Verified |
| 41 | Lecture 41: Performance-Driven Design Flow | Download Verified |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download Verified |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download Verified |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download Verified |
| 45 | Lecture 45 : Design Rule Check | Download Verified |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download Verified |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download Verified |
| 48 | Lecture 48 : | Download Verified |
| 49 | Lecture 49 : | Download Verified |
| 50 | Lecture 50 : | Download Verified |
| 51 | Lecture 51 : | Download Verified |
| 52 | Lecture 52 : | Download Verified |
| 53 | Lecture 53 : Test Pattern Generation | Download Verified |
| 54 | Lecture 54: Design for Testability | Download Verified |
| 55 | Lecture 55: Boundary Scan Standard | Download Verified |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download Verified |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download Verified |
| 58 | Lecture 58 : Low Power VLSI Design | Download Verified |
| 59 | Lecture 59 : Techniques to Reduce Power | Download Verified |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download Verified |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download Verified |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download Verified |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download Verified |
| 64 | Lecture 64 : Summarization of the Course | Download Verified |
| Sl.No | Chapter Name | Gujarati |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | Hindi |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | Malayalam |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | Marathi |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | Tamil |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |
| Sl.No | Chapter Name | Telugu |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Design Representation | Download |
| 3 | Lecture 3: VLSI Design Styles (Part 1) | Download |
| 4 | Lecture 4: VLSI Design Styles (Part 2) | Download |
| 5 | Lecture 5: VLSI Physical Design Automation (Part 1) | Download |
| 6 | Lecture 6: VLSI Physical Design Automation (Part 2) | Download |
| 7 | Lecture 7: Partitioning | Download |
| 8 | Lecture 8: Floorplanning | Download |
| 9 | Lecture 9: "Floorplanning Algorithms | Download |
| 10 | Lecture 10: Pin Assignment | Download |
| 11 | Lecture 11: Placement (Part 1) | Download |
| 12 | Lecture 12: Placement (Part 2) | Download |
| 13 | Lecture 13: Placement (Part 3) | Download |
| 14 | Lecture 14: Placement (Part 4) | Download |
| 15 | Lecture 15: Grid Routing (Part 1) | Download |
| 16 | Lecture 16: Grid Routing (Part 2) | Download |
| 17 | Lecture 17: Grid Routing (Part 3) | Download |
| 18 | Lecture 18: Global Routing (Part 1) | Download |
| 19 | Lecture 19: Global Routing (Part 2) | Download |
| 20 | Lecture 20 : Detailed Routing (Part 1) | Download |
| 21 | Lecture 21: Detailed Routing (Part 2) | Download |
| 22 | Lecture 22: Detailed Routing (Part 3) | Download |
| 23 | Lecture 23 : Detailed Routing (Part 4) | Download |
| 24 | Lecture 24 : Clock Design (Part 1) | Download |
| 25 | Lecture 25 : Clock Design (Part 2) | Download |
| 26 | Lecture 26 : Clock Design (Part 3) | Download |
| 27 | Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) | Download |
| 28 | Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) | Download |
| 29 | Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) | Download |
| 30 | Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) | Download |
| 31 | Lecture 31: POWER AND GROUND ROUTING | Download |
| 32 | Lecture 32: Time Closure (Part 1) | Download |
| 33 | Lecture 33: Time Closure (Part 2) | Download |
| 34 | Lecture 34: Time Closure (Part 3) | Download |
| 35 | Lecture 35: Time Closure (Part 4) | Download |
| 36 | Lecture 36: Time Closure (Part 5) | Download |
| 37 | Lecture 37: Timing Driven Placement | Download |
| 38 | Lecture 38: Timing Driven Routing | Download |
| 39 | Lecture 39: Physical Synthesis (Part 1) | Download |
| 40 | Lecture 40 : Physical Synthesis (Part 2) | Download |
| 41 | Lecture 41: Performance-Driven Design Flow | Download |
| 42 | Lecture 42 : Miscellaneous Approaches to Timing Optimization | Download |
| 43 | Lecture 43 :Interconnect Modeling (Part 1) | Download |
| 44 | Lecture 44 : Interconnect Modeling (Part 2) | Download |
| 45 | Lecture 45 : Design Rule Check | Download |
| 46 | Lecture 46 : Layout Compaction (Part 1) | Download |
| 47 | Lecture 47 : Layout Compaction (Part 2) | Download |
| 48 | Lecture 48 : | Download |
| 49 | Lecture 49 : | Download |
| 50 | Lecture 50 : | Download |
| 51 | Lecture 51 : | Download |
| 52 | Lecture 52 : | Download |
| 53 | Lecture 53 : Test Pattern Generation | Download |
| 54 | Lecture 54: Design for Testability | Download |
| 55 | Lecture 55: Boundary Scan Standard | Download |
| 56 | Lecture 56: Built-in Self-Test (Part 1) | Download |
| 57 | Lecture 57: Built-in Self-Test (Part 2) | Download |
| 58 | Lecture 58 : Low Power VLSI Design | Download |
| 59 | Lecture 59 : Techniques to Reduce Power | Download |
| 60 | Lecture 60 : Gate Level Design for Low Power (Part 1) | Download |
| 61 | Lecture 61 : Gate Level Design for Low Power (Part 2) | Download |
| 62 | Lecture 62 : Other Low Power Design Techniques | Download |
| 63 | Lecture 63 : Algorithmic Level Techniques for Low Power Design | Download |
| 64 | Lecture 64 : Summarization of the Course | Download |