| Module Name | Download |
|---|---|
| noc18_cs54_Assignment1 | noc18_cs54_Assignment1 |
| noc18_cs54_Assignment10 | noc18_cs54_Assignment10 |
| noc18_cs54_Assignment11 | noc18_cs54_Assignment11 |
| noc18_cs54_Assignment12 | noc18_cs54_Assignment12 |
| noc18_cs54_Assignment13 | noc18_cs54_Assignment13 |
| noc18_cs54_Assignment2 | noc18_cs54_Assignment2 |
| noc18_cs54_Assignment3 | noc18_cs54_Assignment3 |
| noc18_cs54_Assignment4 | noc18_cs54_Assignment4 |
| noc18_cs54_Assignment5 | noc18_cs54_Assignment5 |
| noc18_cs54_Assignment6 | noc18_cs54_Assignment6 |
| noc18_cs54_Assignment7 | noc18_cs54_Assignment7 |
| noc18_cs54_Assignment8 | noc18_cs54_Assignment8 |
| noc18_cs54_Assignment9 | noc18_cs54_Assignment9 |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction | Download To be verified |
| 2 | Modeling Techniques – 1 | Download To be verified |
| 3 | Modeling Techniques – 2 | Download To be verified |
| 4 | Hardware/Software Partitioning | Download To be verified |
| 5 | Introduction to Hardware Design | Download To be verified |
| 6 | Hardware Architectural Synthesis – 1 | Download To be verified |
| 7 | Hardware Architectural Synthesis – 2 | Download To be verified |
| 8 | Hardware Architectural Synthesis – 3 | Download To be verified |
| 9 | Hardware Architectural Synthesis – 4 | Download To be verified |
| 10 | Hardware Architectural Synthesis – 5 | Download To be verified |
| 11 | Hardware Architectural Synthesis – 6 | Download To be verified |
| 12 | Hardware Architectural Synthesis – 7 | Download To be verified |
| 13 | System Level Analysis | Download To be verified |
| 14 | Uniprocessor Scheduling – 1 | Download To be verified |
| 15 | Uniprocessor Scheduling – 2 | Download To be verified |
| 16 | Multiprocessor Scheduling – 1 | Download To be verified |
| 17 | Multiprocessor Scheduling – 2 | Download To be verified |
| 18 | Introduction and Basic Operators of Temporal Logic | Download To be verified |
| 19 | Syntax and Semantics of CTL | Download To be verified |
| 20 | Equivalence between CTL formulas | Download To be verified |
| 21 | Model Checking Algorithm | Download To be verified |
| 22 | Binary Decision Diagram | Download To be verified |
| 23 | Use of OBDDs for State Transition System | Download To be verified |
| 24 | Symbolic Model Checking | Download To be verified |
| 25 | Introduction to Digital VLSI Testing | Download To be verified |
| 26 | Automatic Test Pattern Generation (ATPG) | Download To be verified |
| 27 | Scan Chain based Sequential Circuit Testing | Download To be verified |
| 28 | "Software-Hardware Co-validation Fault Models and High Level Testing for Complex Embedded Systems" | Download To be verified |
| 29 | Testing for embedded cores | Download To be verified |
| 30 | Bus and Memory Testing | Download To be verified |
| 31 | Testing for advanced faults in Real time Embedded Systems | Download To be verified |
| 32 | BIST for Embedded Systems | Download To be verified |
| 33 | Concurrent Testing for Fault tolerant Embedded Systems - 1 | Download To be verified |
| 34 | Concurrent Testing for Fault tolerant Embedded Systems - 2 | Download To be verified |
| 35 | Testing for Re-programmable hardware | Download To be verified |
| 36 | Interaction Testing between Hardware and Software | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |