| Module Name | Download | Description | Download Size |
|---|---|---|---|
| Introduction | Module 1 | module1 | 891 |
| Scheduling, Allocation and Binding | Module 2 | module2 | 1136 |
| Logic Optimization and Synthesis | Module3 | module3 | 1210 |
| Temporal Logic | Module4 | module4 | 625 |
| Verification Techniques | Module5 | module5 | 1026 |
| Binary Decision Diagram | Module6 | module6 | 583 |
| Introduction to Digital Testing | Module7 | module7 | 1275 |
| Fault Simulation and Testability Measures | Module8 | module8 | 1372 |
| Combinational Circuit Test Pattern Generation | Module9 | module9 | 794 |
| Sequential Circuit Testing and Scan Chains | Module10 | module10 | 931 |
| Built in Self test (BIST) | Module11 | module11 | 725 |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction to Digital VLSI Design Flow | Download Verified |
| 2 | High Level Design Representation | Download Verified |
| 3 | Transformations for High Level Synthesis | Download Verified |
| 4 | Introduction to HLS: Scheduling, Allocation and Binding Problem | Download Verified |
| 5 | Scheduling Algorithms-1 | Download Verified |
| 6 | Scheduling Algorithms-2 | Download Verified |
| 7 | Binding and Allocation Algorithms | Download Verified |
| 8 | Two level Boolean Logic Synthesis-1 | Download Verified |
| 9 | Two level Boolean Logic Synthesis-2 | Download Verified |
| 10 | Two level Boolean Logic Synthesis-3 | Download Verified |
| 11 | Heuristic Minimization of Two-Level Circuits | Download Verified |
| 12 | Finite State Machine Synthesis | Download Verified |
| 13 | Multilevel Implementation | Download Verified |
| 14 | Introduction to formal methods for design verification | Download Verified |
| 15 | Temporal Logic: Introduction and Basic Operators | Download Verified |
| 16 | Syntax and Semantics of CTL | Download Verified |
| 17 | Syntax and Semantics of CTL – Continued | Download Verified |
| 18 | Equivalence between CTL Formulas | Download Verified |
| 19 | Introduction to Model Checking | Download Verified |
| 20 | Model Checking Algorithms I | Download Verified |
| 21 | Model Checking Algorithms II | Download Verified |
| 22 | Model Checking with Fairness | Download Verified |
| 23 | Binary Decision Diagram: Introduction and construction | Download Verified |
| 24 | Ordered Binary Decision Diagram | Download Verified |
| 25 | Operation on Ordered Binary Decision Diagram | Download Verified |
| 26 | Ordered Binary Decision Diagram for State Transition Systems | Download Verified |
| 27 | Symbolic Model Checking | Download Verified |
| 28 | Introduction to Digital VLSI Testing | Download Verified |
| 29 | Functional and Structural Testing | Download Verified |
| 30 | Fault Equivalence | Download Verified |
| 31 | Fault Simulation-1 | Download Verified |
| 32 | Fault Simulation-2 | Download Verified |
| 33 | Fault Simulation-3 | Download Verified |
| 34 | Testability Measures (SCOAP) | Download Verified |
| 35 | Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras | Download Verified |
| 36 | D-Algorithm-1 | Download Verified |
| 37 | D-Algorithm-2 | Download Verified |
| 38 | ATPG for Synchronous Sequential Circuits | Download Verified |
| 39 | Scan Chain based Sequential Circuit Testing-1 | Download Verified |
| 40 | Scan Chain based Sequential Circuit Testing-2 | Download Verified |
| 41 | Built in Self Test-1 | Download Verified |
| 42 | Built in Self Test-2 | Download Verified |
| 43 | Memory Testing-1 | Download Verified |
| 44 | Memory Testing-2 | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |