Master Slave Flip-Flop (S-R)

When $S=1$, $R=1$, $Q$ and $\overline{Q}$ are both 1. Therefore, it is an undefined condition. This can be eliminated by proper feedback.

for the above circuit, the truth table is

$J$	$K$	$Q_{n+1}$
1	1	$\overline{Q_n}$
0	1	0
1	0	1
0	0	$Q_n$

The problem with the circuit shown above is that when clock =1, the feedback will cause oscillatinons and when clock goes zero, the predicting the ouput state is difficult. On the other hand, master slave configuration does not allow oscillation.