Flip-Flops and Latches

An SR latch is shown in figure 13.3. The latch Truth table is shown in the following table. The two inputs, S and R denote ``set'' and ``reset'' respectively. The latch has memory, and the present output is dependent on the state of the latch. Thus the output at $n^{th}$ instant, denoted by $Q_n$ is dependent on output at $(n-1)^{th}$ instant, denoted by $Q_{n-1}$.

Figure 13.3: Construction of a latch from NOR gates

Students should verify the veracity of the truth table from the figure 13.3.

S	R	$Q_n$	$\overline{Q_n}$
1	0	1	0
0	1	0	1
1	1	0	0
0	0	$Q_{n-1}$	$\overline{Q_{n-1}}$

Note that in $SR=11$ state, both $Q_n$ and $\overline{Q_n}$ are 0, which seems absurd. Thus, conventionally, the state $SR=11$ is said to be ``not allowed''.

A similar latch, known as $\overline{S}\overline{R}$ latch is constructed using NAND gates (as opposed to NOR gates for $SR$ latch). The students should again check that the working of the latch coheres with that of the truth table.

Figure 13.4: Construction of a latch from NAND gates

$\overline{S}$	$\overline{R}$	$Q_n$	$\overline{Q_n}$
0	1	1	0
1	0	0	1
0	0	1	1
1	1	$Q_{n-1}$	$\overline{Q_{n-1}}$

To avoid ``race'' between the inputs, to have a control on when the input affects the latch, the circuit 13.5 is often implemented.

Figure 13.5: Circuit to avoid ``race'' condition

The inputs have an effect on the latch only when $C=1$, otherwise, the previous state is maintained. The input $C$ may be a clock, so that whatever transitions in $S$ and $R$ take place before the clock $C$ changes to $1$ do not affect the outputs, and only when the inputs have become stable is the system affected.