Parallel slave port (PSP)

 PIC Microcontroller offers a mechanism by which an 8-bit parallel bidirectional data transfer can be achieved between a PIC  Microcontroller and a PC. PIC Microcontroller's Port-D and Port-E are used in this data transfer. For this data transfer, Port-D of  PIC Microcontroller is configured as a Parallel slave Port (PSP) by setting bit-4 of TRISE Register. The pins of Port-E function as control pins ( , and ) for data transfer.
The connection diagram between PC and the PIC Microcontroller in PSP Mode is shown below.

ADCON1:
Three low significant bits (PCFG2-PCFG0) are set to enable Port-E pins for digital I/O

ADCON1, ADD: 9F H

This register plays a crucial role in PSP configuration and control.  The lower three bits control the data direction of PortE. the upper four bits are used in conjunction with parallel slave port as shown here.

TRISE, ADD: 89 H

As explained, PSP Mode facilitates bidirectional 8-bit parallel data transfer. After ADCON1<b2-b0> and TRISE<b4, b2-b0> bits are set by the user program, PORTD and PORTE are configured for PSP. When PC wants to write an 8-bit data to PIC, it addresses the PIC microcontroller and the I/O address decoding circuit makes go low selecting the PIC chip. PC also makes     (I/O write) pin low and floats the data through its data bus (b7-b0). The data is written to PORTD and IBF flag in TRISE Register is set indicating that a byte is waiting at PORTD input buffer to be read by the PIC. Simultaneously PSPIF flag bit of PIR1 register is set and an interrupt is generated if PSPIE, PEIE and GIE bits have been set (i.e., the peripheral PSP interrupt is enabled.). After the data is read from PORTD, IBF bit automatically becomes zero; however PSPIF bit has to be cleared by software. If a second byte is written by the PC before the first byte is read, the second byte is lost and the IBOV flag in TRISE register is set indicating this loss.

Similarly a byte can also be read by the PC from the PIC microcontroller. When PIC writes a byte to PORTD, OBF flag is set indicating that the byte is waiting to be read by the PC. When the PC reads this bytes, OBF flag in TRISE Register is automatically cleared and the interrupt flag bit PSPIF is set indicating that the byte has been read by the PC from PIC microcontroller.