4.6 Scaling of MOS transistor dimensions

The steady downscaling of transistor dimensions over the past two decades has been the main motivation to the growth of silicon integrated circuits. Channel lengths of 0.25 µum down to 45nm are now the norm. The more an IC is scaled, the higher becomes its packing density, the higher its circuit speed, the lower its power dissipation. However, reducing the source-to-drain spacing (channel length) of a MOSFET has led to undesirable short channel effects. The most undesirable short-channel effect is the reduction in the gate threshold voltage at which device turns on. In constant-field scaling, it was proposed that one could keep short-channel effects under control by scaling down the vertical dimensions and along with the horizontal dimensions, while also proportionately decreasing the applied voltages and increasing the substrate doping concentrations. Since both the device dimensions and device voltages are scaled down by the same factor k, the electric field remains unchanged. Consequently, the currents also are reduced by a factor of k as well. Since the power dissipation is the product of the current and voltage, the power consumption drops by a factor of k² for this scaling. Because the time factor is reduced by a factor of k, the frequency of operation increases by a factor of k.