Before the actual fabrication of transistors and interconnects, it is advantageous if we could predict to a fair degree whether the circuit is going to function, how much time it would take to perform the operations, how much power it is going to dissipate etc. One can use simulation tools to characterize a particular circuit. The simulations are based on circuit/system models. In this chapter, the focus is to develop simple models that enable one to understand the system performance. To develop models, one should have physical insights of circuit behavior and the fabrication and this knowledge will help the designer to change the circuit to function it better. A fully-fledged model takes into account the parasitic capacitance, resistance, and the inductance effects of the devices and interconnects.

In the previous chapter, we have discussed the fabrication of passive components like resistors, capacitors and active transistors and wires that connect them in CMOS technology. Though the basic properties of transistors are important for logic design; a high performance design requires the consideration of parasitic circuit elements - capacitance and resistance. These parasitics are created as by-products of the fabrication process. With the introduction of deep submicron semiconductor technologies, these parasitics start to dominate the speed, energy consumption and reliability considerations of the ICs. In the following sections, we discus the estimation of resistance and capacitance of interconnects.