Although the highly doped substrate in an epi-CMOS technology is an effective ground for a back side wafer contact, careful design is required to achieve its full benefit for a low resistance topside substrate contact. A square topside substrate contact with an edge dimension compared to the epi-layer thickness can add kilo ohms of series resistance to the substrate path. Consequently, topside substrate contacts should have larger areas. One means of satisfying this requirement and providing maximum dispersal of substrate current is to place a substrate contact ring around the edge of the chip. Such a ring can reduce the lateral bypass resistance below 1 ohm.

Metal connecting contiguous n and p diffusions across their metallurgical junction, forms a butted contact. Such a contact can be used to minimize the emitter/base bypass resistances of a parasitic bipolar.

Process techniques for controlling latch up divide into two categories-bipolar spoiling and bipolar decoupling. One of the earliest techniques of bipolar spoiling was doping silicon with gold or neutron irradiation to reduce the base minority carrier life time. Another method of spoiling the gain of the vertical parasitic bipolar is to build into the base a retarding electric field to impede base transport. This can be achieved by using a retrograde well, i.e. doping increases in going downward from emitter to collector. Still another technique of bipolar spoiling is the use of schottky barrier source/drains and thus reducing the emitter injection efficiency.