Prevention techniques

We now turn to CMOS design techniques to prevent latch up. They divide into two categories-lay out guidelines and process guidelines. Guard structures, multiple well contacts, substrate contact rings and butted source contacts are some of layout precautions a CMOS designer can adopt to avoid latch up. Guard ring structures have been used for many years to decouple one parasitic bipolar from another. These guards are used to collect injected minority carriers before they can cause a problem. A minority carrier guard ring can be an additional well diffusion e.g. n⁺ rings is placed between a parasitic emitter and the n-well. It collects some electrons and remaining electrons only reach the n-well. The guard rings could be deeper surrounding the n type parasitic emitter and such a configuration virtually eliminates electron current flow to the well. The guard rings should not be opposite type source/drain diffusion so that the guard ring itself does not contain parasitic transistors.

Since majority carrier currents flowing through the well are accompanied by voltage drops that can cause the vertical parasitic transistor to turn on, designer should limit the resistance along these ohmic paths. This can be accomplished by providing multiple well contacts to the well using metal lines. Source/drain diffusion by itself provides a sheet resistance at least two orders of magnitude lower than the well's, and its sheet resistance can be lowered still further by frequent contacting with a metal line.