As shown in Fig. 3.69, the p+ region of the p-transistor, the n-well and the p-substrates form a vertical parasitic pnp transistor Q1. When forward biased any P⁺ diffusion can serve as an emitter and inject holes into the n-well base. The reverse biased junction formed by the n-well and substrate then collects the unrecombined holes. The n-well, the p-substrate and the N⁺ source of the n-transistor forms another parasitic npn transistor Q2. In this case electrons are injected from an N⁺ diffusion into the substrate can be collected by the reverse biased n-well. There exist two resistors R well and R sub due to the resistive drop in the well area and the substrate area. Q1 and Q2 form a semiconductor controlled rectifier (SCR), a PNPN circuit as shown in Fig.3.70. Positive gate current switches the device from high to low impedance, negative gate current from low to high. If R_well and/or R_sub are not 0, and for some reason (e.g. power up, current spike etc), Q1 or Q2 are forced to conduct, V_DD will be shorted to ground through the small resistances and the transistors. Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across R_well and R_sub. The only way to get out of this mode is to turn the power off. This condition is known as latch-up.