A further improvement of this technique is the use of a low-doped drain (LDD) structure. As an example, we consider the structure shown in Figure. Here a first shallow implant is used to contact the inversion layer underneath the gate. The shallow implant causes only a small overlap between the gate and source/drain regions. After adding a sidewall to the gate a second deep implant is added to the first one. This deep implant has a low sheet resistance and adds a minimal series resistance. The combination of the two implants therefore yields a minimal overlap capacitance and low access resistance.

In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). The main advantage of CMOS over NMOS and bipolar technology is the much smaller power dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.

The most important CMOS gate is the CMOS inverter. It consists of only two transistors, a pair of one N-type and one P-type transistor. There are again a large number of different CMOS technologies. For example, it is possible to start with an n-type substrate suitable for the p-MOSFET's and to create a sufficiently deep p-type region in areas where n-channel MOSFET's are required. This is known as a p-well technology. The opposite choice of a p-type substrate and creation of an n-well is also possible.