The next development along the axis of the behavioural domain happens to be the finite state machines (FSMs) which are realized at the structural plane by functional modules such as registers, adders, multipliers and arithmetic logic units (ALUs). The automatic placement and routing of these modules are then done on the physical plane with an objective of minimizing the area occupied by the interconnects and signal delay. Next phase of refinement on the behavioural level is the behavioural description of the module. At the structural level, the target chip is now described in terms of the logic gates (or leaf cells ) which can be placed and interconnected using a cell placement and routing program. The last major refinement at the behavioural plane is concerned with the detailed Boolean description of the leaf cells followed by a transistor level realization of the leaf cells and mask generation . Actually, the leaf cells are pre-designed at the transistor level in the standard-cell based design style, and stored in a library for logic implementation.