Similarly for a CMOS to TTL interface, one need to make sure that the CMOS low-state output is less than 0.8 V and the high-state out is greater than 2 V. Additionally, TTL operates with a low sate input current of ~1.6 mA which is a far too much current for a CMOS device to sink without entering the TTL indeterminate region. Therefore the solution would be to use a CMOS/TTL buffer.

Integrated Injection Logic ( IIL , I²L )

Integrated Injection Logic eliminates the need for any resistors, capacitors or transistor isolation. This enables an extremely compact logic circuit to be formed which has low power consumption while maintaining the normal speed of transistor-transistor logic. I²L is built with multiple collector bipolar junction transistors. Although the logic levels are very close (High: 0.7V, Low: 0.2V), I²L has high noise immunity because it operates by current instead of voltage. It is also known as merged-transistor logic.

Emitter Coupled Logic (ECL)

Emitter coupled logic (ECL) gates use differential amplifier configurations at the input stage. (ECL) is a non saturated logic, which means that transistors are prevented from going into deep saturation, thus eliminating storage delays. In other words, the transistor is switched on, but not completely on. This is the fastest logic family. ECL circuits operate using a negative 5.2 V supply and the voltage level for high is -0.9 V and for low is -1.7V; thus biggest problem with ECL is a poor noise margin.