Alternatively, the output of the circuit can be evaluated by substituting values directly into the logic equation.

For example, when A = 1, B = 1, C = 1, D = 0
then Y = AB + CD = 1 . 1 + 1. 0 = 1 + 0 = 1

This can then be repeated for all other input combinations.

The analysis is followed by synthesis i.e. we will consider how to design and implement a logic circuit to enable it to perform the desired specified operation. In this instance, we start with the equation and determine circuit to implement. For example consider the logic function

X = AB + CDE

This is composed of two terms, AB and CDE . The first term is formed by ANDing A and B and the second term is formed by ANDing together C , D and E . These two terms are then ORed together. This can then be implemented using the AND and OR gates, as shown in Fig. 4. Generally, as the number of levels are increased, the overall delay is increased due to the contribution of propagation delays at each gate.