Target Machine
. Byte addressable with 4 bytes per word
. It has n registers R0 , R1 , ..., R n-l
. Two address instructions of the form
opcode source, destination
. Usual opcodes like move, add, sub etc.
. Addressing modes
| MODE |
FORM |
ADDRESS
|
| Absolute |
M |
M
|
| register |
R |
R |
| index |
c(R) |
c+cont(R)
|
| indirect register |
*R |
cont(R)
|
| indirect index |
*c(R) |
cont(c+cont(R))
|
| literal |
#c |
c
|
| |
|
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Familiarity with the target machine and its instruction set is a prerequisite for designing a good code generator. Our target computer is a byte addressable machine with four bytes to a word and n general purpose registers, R 0 , R1 ,..Rn-1 . It has two address instructions of the form
op source, destination
In which op is an op-code, and source and destination are data fields. It has the following op-codes among others:
MOV (move source to destination)
ADD (add source to destination)
SUB (subtract source from destination)
The source and destination fields are not long enough to hold memory addresses, so certain bit patterns in these fields specify that words following an instruction contain operands and/or addresses. The address modes together with their assembly-language forms are shown above.
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