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Synchronization Support in OS/ISA
- Synchronization code can be written using locks
while (1) {
Non critical code
Acquire Lock
Critical Section Code
Release Lock
}
- Implementation of Lock require support from the ISA
- TestAndSet instruction, Swap instruction
- OS may provide system calls to
- Acquire lock or release lock.
- For preemptive OS kernels, hard to implement these calls
Solutions for Multi-processes
boolean waiting[n], lock;
waiting[i] = TRUE;
key = TRUE;
while (waiting[i] && key) key = TestAndSet(&lock);
waiting[i] = FALSE;
// Critical Section
j = (i+1)%n;
while ((j != i) && waiting[j]==FALSE) j = (j+1)%n;
if (j==i) lock=FALSE; else waiting[j] = FALSE;
// Remainder Section |
Multiprocessor Issues
- Multiple processors share a single bus.
- Arbitration is for bus cycles
- Atomicity across processors is at the granularity of bus cycle.
- TestAndSet or Swap instructions require
- At least one read and one write cycle
- Bus arbitration logic has to be instructed to give bus for two cycles.
- Lock instruction prefix in Pentium
- For example lock xchg %ax, mem16
- Lock instruction causes an arbitration sequence to be done for the entire instruction.
- Atomic instruction execution across multiple processors
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