Addressing a Cache

• An example
  • PA is 32 bits
  • Cache line is 64 bytes: block offset is 6 bits
  • Number of cache lines is 512: index is 9 bits
  • So tag is the remaining bits: 17 bits
  • Total size of the cache is 512*64 bytes i.e. 32 KB
  • Each cache line contains the 64 byte data, 17-bit tag, one valid/invalid bit, and several state bits (such as shared, dirty etc.)
  • Since both the tag and the index are derived from the PA this is called a physically indexed physically tagged cache

Set Associative Cache

• The example assumes one cache line per index
  • Called a direct-mapped cache
  • A different access to a line evicts the resident cache line
  • This is either a capacity or a conflict miss
• Conflict misses can be reduced by providing multiple lines per index
• Access to an index returns a set of cache lines
  • For an n-way set associative cache there are n lines per set
• Carry out multiple tag comparisons in parallel to see if any one in the set hits