Implications on Software

• A tall memory hierarchy
  • Each core could run multiple threads
    • Each core in Niagara runs four threads
  • Within core, threads communicate through private cache (fastest)
  • Across cores communication happens through shared L2 cache or coherence controller (if tiled)
  • Multiple such chips can be connected over a scalable network
    • Adds one more level of memory hierarchy
• A very non-uniform access stack

Research Directions

• Hexagon of puzzles
  • Running single-threaded programs efficiently on this sea of cores
  • Managing energy envelope efficiently
  • Allocating shared cache efficiently
  • Allocating shared off-chip bandwidth and memory banks efficiently
  • Making parallel programming easy
    • Transactional memory
    • Speculative parallelization
  • Verification of hardware and parallel software and tolerate faults