Module 8: Memory Consistency Models and Case Studies of Multi-core
  Lecture 15: Memory Consistency Models and Case Studies of Multi-core
 


Case Studies

CMP

  • CMP is the mantra of today's microprocessor industry
    • Intel's dual-core Pentium 4: each core is still hyperthreaded (just uses existing cores)
    • Intel's quad-core Whitefield is coming up in a year or so
    • For the server market Intel has announced a dual-core Itanium 2 (code named Montecito); again each core is 2-way threaded
    • AMD has released dual-core Opteron in 2005
    • IBM released their first dual-core processor POWER4 circa 2001; next-generation POWER5 also uses two cores but each core is also 2-way threaded
    • Sun's UltraSPARC IV (released in early 2004) is a dual-core processor and integrates two UltraSPARC III cores

Why CMP?

  • Today microprocessor designers can afford to have a lot of transistors on the die
    • Ever-shrinking feature size leads to dense packing
    • What would you do with so many transistors?
    • Can invest some to cache, but beyond a certain point it doesn't help
    • Natural choice was to think about greater level of integration
    • Few chip designers decided to bring the memory and coherence controllers along with the router on the die
    • The next obvious choice was to replicate the entire core; it is fairly simple: just use the existing cores and connect them through a coherent interconnect