RISC Processors

• All these atomic instructions deviate from the RISC line
  • Instruction needs a load as well as a store
• Also, it would be great if we can offer a few simple instructions with which we can build most of the atomic primitives
  • Note that it is impossible to build atomic fetch & inc with xchg instruction
• MIPS, Alpha and IBM processors support a pair of instructions: LL and SC
  • Load linked and store conditional

LL/SC

• Load linked behaves just like a normal load with some extra tricks
  • Puts the loaded value in destination register as usual
  • Sets a load_linked bit residing in cache controller to 1
  • Puts the address in a special lock_address register residing in the cache controller
• Store conditional is a special store
  • sc reg , addr stores value in reg to addr only if load_linked bit is set; also it copies the value in load_linked bit to reg and resets load_linked bit
• Any intervening “operation” (e.g., bus transaction or cache replacement) to the cache line containing the address in lock_address register clears the load_linked bit so that subsequent sc fails