Back to Shared Bus

• Centralized shared bus makes it easy to support SC
  • Writes and reads are all serialized in a total order through the bus transaction ordering
  • If a read gets a value of a previous write, that write is guaranteed to be complete because that bus transaction is complete
  • The write order seen by all processors is the same in a write through system because every write causes a transaction and hence is visible to all in the same order
  • In a nutshell, every processor sees the same total bus order for all memory operations and therefore any bus-based SMP with write through caches is SC
• What about a multiprocessor with writeback cache?
  • No SMP uses write through protocol due to high BW

Snoopy Protocols

• No change to processor or cache
  • Just extend the cache controller with snoop logic and exploit the bus
• We will focus on writeback caches only
  • Possible states of a cache line: Invalid (I), Shared (S), Modified or dirty (M), Clean exclusive (E), Owned (O); every processor does not support all five states
  • E state is equivalent to M in the sense that the line has permission to write, but in E state the line is not yet modified and the copy in memory is the same as in cache; if someone else requests the line the memory will provide the line
  • O state is exactly same as E state but in this case memory is not responsible for servicing requests to the line; the owner must supply the line (just as in M state)
  • Stores really read the memory (as opposed to write)