Module 6: Shared Memory Multiprocessors: Consistency and Coherence
  Lecture 11: Introduction to Snoopy Coherence
 


SC Example

  • Consider the following example

    P0: A=1; print B;
    P1: B=1; print A;

  • Possible outcomes for an SC machine
    • (A, B) = (0,1); interleaving: B=1; print A; A=1; print B
    • (A, B) = (1,0); interleaving: A=1; print B; B=1; print A
    • (A, B) = (1,1); interleaving: A=1; B=1; print A; print B
      A=1; B=1; print B; print A

 

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    • (A, B) = (0,0) is impossible: read of A must occur before write of A and read of B must occur before write of B i.e. print A < A=1 and print B < B=1, but A=1 < print B and B=1 < print A; thus print B < B=1 < print A < A=1 < print B which implies print B < print B, a contradiction

Implementing SC

  • Two basic requirements
    • Memory operations issued by a processor must become visible to others in program order
    • Need to make sure that all processors see the same total order of memory operations: in the previous example for the (0,1) case both P0 and P1 should see the same interleaving: B=1; print A; A=1; print B
  • The tricky part is to make sure that writes become visible in the same order to all processors
    • Write atomicity : as if each write is an atomic operation
    • Otherwise, two processors may end up using different values (which may still be correct from the viewpoint of cache coherence, but will violate SC)