Cache Coherence

• Formal definition
  • A memory system is coherent if the values returned by reads to a memory location during an execution of a program are such that all operations to that location can form a hypothetical total order that is consistent with the serial order and has the following two properties:
    1. Operations issued by any particular processor perform according to the issue order
    2. The value returned by a read is the value written to that location by the last write in the total order
  • Two necessary features that follow from above:
    1. Write propagation: writes must eventually become visible to all processors
    2. Write serialization: Every processor should see the writes to a location in the same order (if I see w1 before w2, you should not see w2 before w1)

Bus-based SMP

• Extend the philosophy of uniprocessor bus transactions
  • Three phases: arbitrate for bus, launch command (often called request) and address, transfer data
  • Every device connected to the bus can observe the transaction
  • Appropriate device responds to the request
  • In SMP, processors also observe the transactions and may take appropriate actions to guarantee coherence
  • The other device on the bus that will be of interest to us is the memory controller (north bridge in standard mother boards)
  • Depending on the bus transaction a cache block executes a finite state machine implementing the coherence protocol