Module 5: Performance Issues in Shared Memory and Introduction to Coherence
  Lecture 10: Introduction to Coherence
 


Shared Memory Multiprocessors

Four Organizations

  • Shared cache

  • The switch is a simple controller for granting access to cache banks
  • Interconnect is between the processors and the shared cache
  • Which level of cache hierarchy is shared depends on the design: Chip multiprocessors today normally share the outermost level (L2 or L3 cache)
  • The cache and memory are interleaved to improve bandwidth by allowing multiple concurrent accesses
  • Normally small scale due to heavy bandwidth demand on switch and shared cache
  • Bus-based SMP

  • Scalability is limited by the shared bus bandwidth
  • Interconnect is a shared bus located between the private cache hierarchies and memory controller
  • The most popular organization for small to medium-scale servers
  • Possible to connect 30 or so processors with smart bus design
  • Bus bandwidth requirement is lower compared to shared cache approach
  • Why?