Out-of-order Multiple Issue

• Some hardware nightmares
  • Complex issue logic to discover independent instructions
  • Increased pressure on cache
    • Impact of a cache miss is much bigger now in terms of lost opportunity
    • Various speculative techniques are in place to “ignore” the slow and stupid memory
  • Increased impact of control dependence
    • Must feed the processor with multiple correct instructions every cycle
    • One cycle of bubble means lost opportunity of multiple instructions
  • Complex logic to verify

Moore's Law

• Number of transistors on-chip doubles every 18 months
  • So much of innovation was possible only because we had transistors
  • Phenomenal 58% performance growth every year
• Moore's Law is facing a danger today
  • Power consumption is too high when clocked at multi-GHz frequency and it is proportional to the number of switching transistors
• Wire delay doesn't decrease with transistor size